Field of the Invention
The present disclosure relates to semiconductor devices, and more particularly to a semiconductor device including an ESD (Electro Static Discharge) protection element.
Description of the Background Art
With the recent improvements in function and performance of semiconductor devices, a need has arisen for multi-pin semiconductor devices having more than several thousand I/O pins (input/output pins). Accordingly, the area of each I/O block is increasingly having a greater influence on size and cost reductions of the entire semiconductor device. Elements which constitute a high percentage of the area of an I/O block are an electrostatic discharge protection element (ESD protection element) and a driver element of high drive power.
In this respect, a technique of adding resistance in order to improve the protection tolerance of an ESD protection element (ESD tolerance) is commonly employed.
For example, Japanese Patent Laying-Open No. 2005-183661 discloses a technique of adding a ballast resistor as resistance. Specifically, there is disclosed a technique of isolating a diffusion layer by STI (Shallow Trench Isolation) and providing the isolated diffusion layer with a resistive component to form a ballast resistor.